In an electronic data processing system, data are transmitted from the data sending terminals to receiving terminals from time to time. Some devices are only data sources or data sinks; however, some devices may act as both data source and data sink. For example, the CPU and the DRAM of modern data processing systems are data both sending and receiving terminals.
Some data sending terminal, such as CPU, and data receiving terminals, such as the DRAM of a memory device, are commercially available from the system design point of view. The system designer must design the system circuits to meet the specifications inherent in the vendor's devices as well as the specifications the target data processing system intends to achieve.
While designing a data processing system, there are at least two criteria to be met on the side of the data receiving terminal. First, the specification of the data receiving terminal, such as the CPU, requires a minimum value the HOLD time. The HOLD time (t.sub.h) is the time span of data is held valid after receiving completion of the data. Secondly, the specification of the data receiving terminal requires a minimum value of SETUP time. The SETUP time (t.sub.s) is the time span of data existing validly before the commencement of receiving data.
Referring to FIG. 1, the timing diagram of a typical memory read cycle has been depicted. In FIG. 1, the ALE (Address Latch Enable) is a signal which notifies the memory device the address bus is starting a bus cycle, ADDRESS signal tells to which location of tile memory device data access is desired, and MEMR is a memory read signal to the memory device. The shown t.sub.h is the HOLD time and the t.sub.s is the SETUP time of the data receiving terminal.
In some instances where the minimum HOLD time of a data receiving terminal is not met by the data sent by the data sending terminal, an off-the-shelf buffer/driver such as TTL 74646 may be implemented between the receiving terminal and the sending terminal. Alternatively, instead of using a commercial component such as TTL 74646, a circuit block, functioning as TTL 74646, on the system board designed by the System designer may do the same work. The buffer/driver first latches the data, and then re-transmits the data to the data receiving terminal. The data being sent will be held valid by the buffer/driver until the HOLD time of the receiving terminal has been met. This prior art arrangement of the buffer/driver, shown in FIG. 2(a), however, would cause delay of the data transmission, due to the serial configuration of the buffer/driver, resulting in the shorter SETUP time for the data receiving terminal. This shorter SETUP time will not always satisfy the requirement on the SETUP time of the data receiving terminal. The timing diagram of the prior art arrangement of buffer/driver is shown in FIG. 2(b).
Another approach to solve the above problem is to implement a circuit in the data processing system to generate a NOREADY signal forcing the data sending terminal to hold the data valid until the minimum HOLD time of the data receiving terminal has been satisfied. In the case of the CPU, the NOREADY signal is input to the READY pin of the CPU forcing the CPU to insert wait states until the minimum HOLD time requirement of the data receiving terminal has been met. This is also a very common practice. However, this practice slows down the speed of the central processing unit and is not recommended in high speed data processing system design.